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JEDEC JESD241 PDF
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Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities
| Published by | Publication Date | Number of Pages |
| JEDEC | 12/01/2015 | 32 |
JEDEC JESD241 – Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document.
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