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JEDEC JEP147 PDF
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PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
| Published by | Publication Date | Number of Pages |
| JEDEC | 10/01/2003 | 11 |
JEDEC JEP147 – PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)
This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote – usually found around the specification of pin parasitics – to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.
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